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Design of approximate adders and multipliers for error tolerant image processing

  • Published:2020-02 Issue: Volume:72 Page:102940
  • ISSN:0141-9331
  • Container-title:Microprocessors and Microsystems
  • language:en
  • Short-container-title:Microprocessors and Microsystems

Author:

Anusha G.,Deepa P.

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Software

Reference20 articles.

1. Investigating the impact of logic and circuit implementation for full adder performance;Purohit;IEEE Trans. VLSI Syst.,2012

2. Digital Design and Computer Architecture;Harris,2012

3. IMPACT imprecise adders for low-power approximate computing;Gupta,2011

4. An enhanced low power high speed adder for error-tolerant application;Zhu,2009

5. Design of low power high-speed truncation error tolerant adders and its application in DSP;Zhu,2010

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1. Low Power Multiplier Using Approximate Adder for Error Tolerant Applications;IETE Journal of Research;2024-09-11

2. APPAs: fast and efficient approximate parallel prefix adders and multipliers;The Journal of Supercomputing;2024-07-24

3. Image Multiplication Using Novel 4:1 Approximate Compressor*;IETE Journal of Research;2024-07-11

4. Approximate Floating Point Precise Carry Prediction Adder for FIR Filter Applications;Circuits, Systems, and Signal Processing;2024-06-29

5. Design of Efficient Approximate Unsigned Multiplier using VariousApproximate Compressor Configurations;2024 International Conference on Smart Systems for Electrical, Electronics, Communication and Computer Engineering (ICSSEECC);2024-06-28
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