Image Multiplication Using Novel 4:1 Approximate Compressor*-Reference-Cited by-同舟云学术

Image Multiplication Using Novel 4:1 Approximate Compressor*

Published:2024-07-11 Issue: Volume: Page:1-13
ISSN:0377-2063
Container-title:IETE Journal of Research
language:en
Short-container-title:IETE Journal of Research

Author:

Karunamurthi Saranya¹,Jammu Bhaskara Rao²,Bodasingi Nalini³,Veeramachaneni Sreehari⁴,Mahammad S Noor⁵

Affiliation:

1. Department of Electrical & Electronics Engineering, Dr. Mahalingam College of Engineering & Technology, Pollachi, Tamil Nadu, 642003, India

2. Department of ECE, GVP College of Engineering (A), Visakhapatnam, Andhra Pradesh, 530048, India

3. Department of ECE, JNTU GV, Vizianagaram, Andhra Pradesh, 535003, India

4. Department of Electronics & Communication Engineering, Gokaraju Rangaraju Institute of Engineering & Technology, Hyderabad, Telangana, 500090, India

5. Department of Computer Science and Engineering, Indian Institute of InformationTechnology Design and Manufacturing (IIITDM) Kancheepuram, Chennai, Tamil Nadu, 600127, India

Publisher

Informa UK Limited

Link

https://www.tandfonline.com/doi/pdf/10.1080/03772063.2024.2369258

Reference22 articles.

1. Design of approximate adders and multipliers for error tolerant image processing

2. Delay and area efficient approximate multiplier using reverse carry propagate full adder

3. K. C. Pathak J. N. Sarvaiya A. D. Darji S. Diwan A. Gangadwala Z. Bhatt and A. Patel “An efficient dadda multiplier using approximate adder ” in 2020 IEEE Region 10 Conference (TENCON) IEEE 2020 pp. 176–181.

4. W. J. Townsend E. E. Swartzlander Jr and J. A. Abraham “A comparison of dadda and wallace multiplier delays ” in Advanced signal processing algorithms architectures and implementations XIII Vol. 5205 International Society for Optics and Photonics 2003 pp. 552–560.