Asynchronous Advanced Encryption Standard Hardware with Random Noise Injection for Improved Side-Channel Attack Resistance

Author:

Kotipalli Siva1ORCID,Kim Yong-Bin2ORCID,Choi Minsu3ORCID

Affiliation:

1. Samsung Electronics, Austin, TX 78754, USA

2. Department of Electrical and Computer Engineering, Northeastern University, Boston, MA 02115, USA

3. Department of Electrical and Computer Engineering, Missouri University of Science & Technology, Rolla, MO 65409, USA

Abstract

This work presents the design, hardware implementation, and performance analysis of novel asynchronous AES (advanced encryption standard) Key Expander and Round Function, which offer increased side-channel attack (SCA) resistance. These designs are based on a delay-insensitive (DI) logic paradigm known as null convention logic (NCL), which supports useful properties for resisting SCAs including dual-rail encoding, clock-free operation, and monotonic transitions. Potential benefits include reduced and more uniform switching activities and reduced signal-to-noise (SNR) ratio. A novel method to further augment NCL AES hardware with random voltage scaling technique is also presented for additional security. Thereby, the proposed components leak significantly less side-channel information than conventional clocked approaches. To quantitatively verify such improvements, functional verification and WASSO (weighted average simultaneous switching output) analysis have been carried out on both conventional synchronous approach and the proposed NCL based approach using Mentor Graphics ModelSim and Xilinx simulation tools. Hardware implementation has been carried out on both designs exploiting a specified side-channel attack standard evaluation FPGA board, called SASEBO-GII, and the corresponding power waveforms for both designs have been collected. Along with the results of software simulations, we have analyzed the collected waveforms to validate the claims related to benefits of the proposed cryptohardware design approach.

Publisher

Hindawi Limited

Subject

Electrical and Electronic Engineering,General Computer Science,Signal Processing

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1. Enhancing Side-Channel Attacks Through X-Ray-Induced Leakage Amplification;2024 Design, Automation & Test in Europe Conference & Exhibition (DATE);2024-03-25

2. Improving FPGA-based Async-logic AES Accelerator with the Integration of Sync-logic Block RAMs;2023 IEEE International Symposium on Circuits and Systems (ISCAS);2023-05-21

3. A Highly Secure FPGA-Based Dual-Hiding Asynchronous-Logic AES Accelerator Against Side-Channel Attacks;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2022-09

4. A SHA-256 Hybrid-Redundancy Hardware Architecture for Detecting and Correcting Errors;Sensors;2022-07-03

5. An Asynchronous-Logic Masked Advanced Encryption Standard (AES) Accelerator and its Side-Channel Attack Evaluations;2022 IEEE International Symposium on Circuits and Systems (ISCAS);2022-05-28

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