A Highly Secure FPGA-Based Dual-Hiding Asynchronous-Logic AES Accelerator Against Side-Channel Attacks-Reference-Cited by-同舟云学术

A Highly Secure FPGA-Based Dual-Hiding Asynchronous-Logic AES Accelerator Against Side-Channel Attacks

Published:2022-09 Issue:9 Volume:30 Page:1144-1157
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Ng Jun-Sheng¹^ORCID,Chen Juncheng¹^ORCID,Chong Kwen-Siong¹^ORCID,Chang Joseph S.¹^ORCID,Gwee Bah-Hwee¹^ORCID

Affiliation:

1. School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore

Funder

National Research Foundation, Singapore, under its National Cybersecurity Research and Development (NCR) Research Program in Assuring Hardware Security by Design in Systems on Chip, SOCure

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx7/92/9874436/09783469.pdf?arnumber=9783469

Reference47 articles.

1. FPGA implementation of compact S-Box for AES algorithm using composite field arithmetic

2. Efficient Dual-Rail Implementations in FPGA Using Block RAMs

3. BCDL: A high speed balanced DPL for FPGA with global precharge and no early evaluation

4. Secured Low Power Overhead Compensator Look-Up-Table (LUT) Substitution Box (S-Box) Architecture

5. A Robust Architectural Approach for Cryptographic Algorithms Using GALS Pipelines

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