Author:
Chen Chung-Ping,Chen Yao-Ping,Wong D. F.
Cited by
13 articles.
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1. Performance-driven Wire Sizing for Analog Integrated Circuits;ACM Transactions on Design Automation of Electronic Systems;2022-12-24
2. Clock Design and Synthesis;Electronic Design Automation for IC Implementation, Circuit Design, and Process Technology;2016-04-14
3. Net-by-Net Wire Optimization;Multi-Net Optimization of VLSI Interconnect;2014-10-16
4. Revisiting automated physical synthesis of high-performance clock networks;ACM Transactions on Design Automation of Electronic Systems;2013-03
5. Reducing expected delay and power in FPGAs using buffer insertion in single-driver wires;Microelectronics Journal;2012-12