Author:
Desai Madhav P.,Cvijetic Radenko,Jensen James
Cited by
5 articles.
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1. Timing–driven variation–aware synthesis of hybrid mesh/tree clock distribution networks;Integration;2013-09
2. Revisiting automated physical synthesis of high-performance clock networks;ACM Transactions on Design Automation of Electronic Systems;2013-03
3. High-performance clock mesh optimization;ACM Transactions on Design Automation of Electronic Systems;2012-06
4. System Wireability;Modeling Microprocessor Performance;1998
5. Layout Optimization;Low Power Design in Deep Submicron Electronics;1997