Dead-block prediction & dead-block correlating prefetchers

Author:

Lai An-Chow1,Fide Cem2,Falsafi Babak3

Affiliation:

1. Electrical & Computer Engineering, Purdue University, West Lafayette, IN

2. Sun Microsystems, 901 San Antonio Rd, Palo Alto, CA

3. Electrical & Computer Engineering, Carnegie Mellon University, Pittsburgh, PA

Abstract

Effective data prefetching requires accurate mechanisms to predict both “which” cache blocks to prefetch and “when” to prefetch them. This paper proposes the Dead-Block Predictors (DBPs), trace-based predictors that accurately identify “when” an Ll data cache block becomes evictable or “dead”. Predicting a dead block significantly enhances prefetching lookahead and opportunity, and enables placing data directly into Ll, obviating the need for auxiliary prefetch buffers. This paper also proposes Dead-Block Correlating Prefetchers (DBCPs), that use address correlation to predict “which” subsequent block to prefetch when a block becomes evictable. A DBCP enables effective data prefetching in a wide spectrum of pointer-intensive, integer, and floating-point applications. We use cycle-accurate simulation of an out-of-order superscalar processor and memory-intensive benchmarks to show that: (1) dead-block prediction enhances prefetching lookahead at least by an order of magnitude as compared to previous techniques, (2) a DBP can predict dead blocks on average with a coverage of 90% only mispredicting 4% of the time, (3) a DBCP offers an address prediction coverage of 86% only mispredicting 3% of the time, and (4) DBCPs improve performance by 62% on average and 282% at best in the benchmarks we studied.

Publisher

Association for Computing Machinery (ACM)

Cited by 23 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Last-Level Cache Insertion and Promotion Policy in the Presence of Aggressive Prefetching;IEEE Computer Architecture Letters;2023-01

2. Dynamic Set Stealing to Improve Cache Performance;2022 IEEE 34th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD);2022-11

3. Applying machine learning to enhance the cache performance using reuse distance;Evolutionary Intelligence;2022-05-27

4. A Categorical Study on Cache Replacement Policies for Hierarchical Cache Memory;Applications of Internet of Things;2020-08-04

5. ECAP: energy‐efficient caching for prefetch blocks in tiled chip multiprocessors;IET Computers & Digital Techniques;2019-08-08

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