PV-Aware Analog Sizing for Robust Analog Layout Retargeting with Optical Proximity Correction

Abstract

For analog integrated circuits (ICs) in nanometer technology nodes, process variation (PV) induced by lithography may not only cause serious wafer pattern distortion, but also result in device mismatch, which can readily ruin circuit performance. Although the conventional optical proximity correction (OPC) operations can effectively improve the wafer image fidelity, an analog circuit without robust device sizes is still highly vulnerable to such a mismatch effect. In this article, a PV-aware sizing-inclusive analog layout retargeting framework, which encloses an efficient hybrid OPC scheme for yield enhancement, is proposed. The device sizes are tuned during the layout retargeting process by using a deterministic circuit-sizing algorithm considering PV conditions. Our hybrid OPC method combines global rule-based OPC with local model-based OPC functions to boost the wafer image quality improvement but without degrading the computational efficiency. The experimental results show that our proposed framework can achieve the best wafer image quality and circuit performance preservation compared to any other alternative approaches.