Variation-Aware Analog Circuit Sizing in Carbon Nanotube
Author:
Affiliation:
1. Memorial University of Newfoundland,Department of Electronic Engineering,St.john’s,Canada
Funder
Natural Sciences and Engineering Research Council of Canada
Canada Foundation for Innovation
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9937201/9937203/09937568.pdf?arnumber=9937568
Reference21 articles.
1. Parasitic-aware GP-based many-objective sizing methodology for analog and RF integrated circuits
2. On Applying Pareto Optimization for Complete Performance Space Modeling of Analog ICs;schreiber;ANALOG 2018 16th GMM/ITG-Symposium dummydata,2018
3. Multi-Objective Optimization Methods for CMOS LC-VCO Design
4. Compact modeling and design optimization of carbon nanotube field-effect transistors for the sub-10nm technology nodes;lee;Proc 73rd Annual Device Research Conference (DRC),2015
5. PV-Aware Analog Sizing for Robust Analog Layout Retargeting with Optical Proximity Correction
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