Affiliation:
1. University of Southern California, Los Angeles, CA, USA
Funder
Intel Hardware Accelerator Research Program
US National Science Foundation
Intel Strategic Research Alliance
Reference22 articles.
1. 2015. Intel Inc. Xeon+FPGA Platform for the Data Center. (2015). https://www. ece.cmu.edu/calcm/carl/lib/exe/fetch.php?media=carl15-gupta.pdf 2015. Intel Inc. Xeon+FPGA Platform for the Data Center. (2015). https://www. ece.cmu.edu/calcm/carl/lib/exe/fetch.php?media=carl15-gupta.pdf
2. Y. H. Chen J. Emer and V. Sze. 2017. Using Dataflow to Optimize Energy Efficiency of Deep Neural Network Accelerators. IEEE Micro 37 3 (2017). Y. H. Chen J. Emer and V. Sze. 2017. Using Dataflow to Optimize Energy Efficiency of Deep Neural Network Accelerators. IEEE Micro 37 3 (2017).
3. Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks
4. Overlap-Save and Overlap-Add Filters: Optimal Design and Comparison
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