Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks-Reference-Cited by-同舟云学术

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Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks

Published:2015-02-22 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
language:
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Author:

Zhang Chen¹,Li Peng²,Sun Guangyu³,Guan Yijin¹,Xiao Bingjun²,Cong Jason⁴

Affiliation:

1. Center for Energy-Efficient Computing and Applications, Peking University, Beijing, China

2. Computer Science Department, University of California, Los Angeles, Los Angeles, USA

3. Center for Energy-Efficient Computing and Applications, Peking University & PKU/UCLA Joint Research Institute in Science and Engineering, Beijing, China

4. Computer Science Department, University of California, Los Angeles, Los Angeles, USA & Center for Energy-Efficient Computing and Applications, Peking University & PKU/UCLA Joint Research Institute in Science and Engineering, Beijing, China

Funder

C-FAR

NSF China

National High Technology Research and Development Program of China

RFDP

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/2684746.2689060

Reference16 articles.

1. A programmable parallel accelerator for learning and classification

2. A dynamically configurable coprocessor for convolutional neural networks

4. Minimizing Computation in Convolutional Neural Networks

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