Dynamic Behavior Predictions for Fast and Efficient Hybrid STT-MRAM Caches

Author:

Sayed Nour1,Mao Longfei2,Tahoori Mehdi B.1

Affiliation:

1. Chair of Dependable Nano Computing, Karlsruhe Institute of Technology (KIT), Karlsruhe, Germany

2. Karlsruhe Institute of Technology (KIT), Karlsruhe, Germany

Abstract

Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) is a promising candidate as a universal on-chip memory technology due to its non-volatility, high density, and scalability. However, high write energy and latency are its major shortcomings, particularly for fast cache applications. High write costs can efficiently be reduced by relaxing the STT-MRAM non-volatility requirements at the expense of significant increase in retention failure and read disturb rates resulting in data corruption. Hybrid STT-MRAM architecture combining non-volatile (NVM) and semi-volatile (SVM) STT-MRAM blocks has been proposed recently, which provides energy-efficiency, high storage capacity, better performance, and high reliability. However, a key and challenging requirement is efficient data mapping and migration between NVM and SVM sub-arrays to maximize the benefits of such hybrid caches. On-the-fly data migration decisions usually depend on the last seen data behavior, as it is assumed to be identical to the next one, which has very limited accuracy for rapidly varying workload behavior. In this article, we propose a simple but effective on-the-fly data management policy, which mainly relies on the supervised learning data-pattern classification for quick and highly accurate prediction of the data behavior in the oncoming execution time. Three prediction approaches are proposed and compared for a maximum and average achieved accuracy of 86% and 75%, respectively. Our data management policies aim to optimally leverage the specific features of NVM (high reliability) and SVM blocks (fast and energy-efficient write) of hybrid STT-MRAM memory with minimal migration costs (i.e., energy and performance overheads). Our experimental evaluation reports that for a hybrid STT-MRAM cache with the proposed prediction techniques, the total energy consumption can be reduced around 10.5%, on average, in comparison to the state-of-the-art.

Funder

22nd IEEE European Test Symposium

ANR/DFG as part of the MASTA project

European Commission under the Horizon-2020 Program as part of the GREAT project

Publisher

Association for Computing Machinery (ACM)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. MRAM-Based Cache System Design and Policy Optimization for RISC-V Multi-Core CPUs;IEEE Transactions on Magnetics;2023-06

2. A Spintronic 2M/7T Computation-in-Memory Cell;Journal of Low Power Electronics and Applications;2022-12-06

3. Time-Dependent Electromigration Modeling for Workload-Aware Design-Space Exploration in STT-MRAM;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2022-12

4. Voltage Tuning for Reliable Computation in Emerging Resistive Memories;2022 IEEE 40th VLSI Test Symposium (VTS);2022-04-25

5. Write-awareness prefetching for non-volatile cache in energy-constrained IoT device;IEICE Electronics Express;2022-02-10

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