Affiliation:
1. University of Toronto
2. University of Toronto, Toronto, Canada
Abstract
As the number of cores integrated on a single chip continues to increase, communication has the potential to become a severe bottleneck to overall system performance. The presence of thread sharing and the distribution of data across cache banks on the chip can result in longdistance communication. Long-distance communication incurs substantial latency that impacts performance; furthermore, this communication consumes significant dynamic power when packets are switched over many Network-on-Chip (NoC) links and routers. Thread migration can mitigate problems created by long distance communication. This article presents Moths, an efficient runtime algorithm that responds automatically to dynamic NoC traffic patterns, providing beneficial thread migration to decrease overall traffic volume and average packet latency. Moths reduces on-chip network latency by up to 28.4% (18.0% on average) and traffic volume by up to 24.9% (20.6% on average) across a variety of commercial and scientific benchmarks.
Funder
Natural Sciences and Engineering Research Council of Canada
Publisher
Association for Computing Machinery (ACM)
Subject
Hardware and Architecture,Software
Cited by
2 articles.
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1. Optimizing memory access traffic via runtime thread migration for on-chip distributed memory systems;The Journal of Supercomputing;2014-06-24
2. Fort-NoCs;Proceedings of the The 51st Annual Design Automation Conference on Design Automation Conference - DAC '14;2014