Fault-tolerant Network-on-Chip based on Fault-aware Flits and Deflection Routing-Reference-Cited by-同舟云学术

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Fault-tolerant Network-on-Chip based on Fault-aware Flits and Deflection Routing

Published:2015-09-28 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 9th International Symposium on Networks-on-Chip
language:
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Author:

Runge Armin¹

Affiliation:

1. Department of Computer Science, Am Hubland, Würzburg, Germany

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/2786572.2786585

Reference24 articles.

1. Designing Reliable Systems from Unreliable Components: The Challenges of Transistor Variability and Degradation

2. Thousand core chips

3. Future of interconnect fabric

4. MD: Minimal path-based fault-tolerant routing in on-Chip Networks

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1. Sixer: A low-overhead, fully-distributed test scheme with guaranteed delivery of packets in networks-on-chip;Microelectronics Reliability;2023-03

2. Optimal port allocation scheme for deflection-routed networks-on-chip;The Journal of Supercomputing;2021-05-10

3. Maximal Connectivity Test with Channel-Open Faults in On-Chip Communication Networks;Journal of Electronic Testing;2020-04-27

4. A Low-Cost Test Solution for Reliable Communication in Networks-on-Chip;Journal of Electronic Testing;2019-04

5. Performance-Aware Test Scheduling for Diagnosing Coexistent Channel Faults in Topology-Agnostic Networks-on-Chip;ACM Transactions on Design Automation of Electronic Systems;2019-03-31

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