Evaluating instruction cache vulnerability to transient errors

Abstract

Recent research shows that microprocessors are increasingly susceptible to transient errors. In order to protect microprocessors cost-effectively, the first step is to accurately understand the impact of transient errors on the system reliability. While many research efforts have been focused on studying the vulnerability of data caches and other on-chip hardware components, instruction caches have received less attention. However, instructions are read every cycle, any undetected or uncorrected soft errors in instructions can lead to erroneous computation, wrong control flow or system crash. This paper studies the instruction cache vulnerability by considering both the raw SRAM rate and the cache vulnerability factor. Based on the concept of cache vulnerability factor, we also investigate the impact of different cache configuration parameters on the reliability of instruction caches. We find that on average 67.5% of instruction cache soft errors can be masked by the I-cache itself without impacting other system components. While quantifying the instruction cache vulnerability itself does not solve the reliability problem of instruction cache against transient errors, we believe this work can provide useful insights for designers to develop cost-effective solutions to protect I-caches and to optimally balance the reliability of instruction caches with other system goals, such as cost, performance and energy.