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On the characterization and optimization of system-level vulnerability for instruction caches in embedded processors

  • Published:2015-11 Issue:8 Volume:39 Page:686-692
  • ISSN:0141-9331
  • Container-title:Microprocessors and Microsystems
  • language:en
  • Short-container-title:Microprocessors and Microsystems

Author:

Wang Shuai,Duan Guangshan

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Software

Reference36 articles.

1. Characterizing system-level vulnerability for instruction caches against soft errors;Wang,2011

2. Techniques to reduce the soft errors rate in a high-performance microprocessor;Weaver,2004

3. IBM experiments in soft fails in computer electronics (1978 - 1994);Ziegler;IBM J. Res. Dev.,1996

4. Modeling the effect of technology trends on the soft error rate of combinational logic;Shivakumar,2002

5. Area efficient architectures for information integrity checking in cache memories;Kim,1999

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