Affiliation:
1. University of Houston, TX
2. Louisiana State University, Baton Rouge, LA
3. East China Normal University, Shanghai, China
Abstract
Mobile devices are quickly becoming the most widely used processors in consumer devices. Since their major power supply is battery, energy-efficient computing is highly desired. In this article, we focus on energy-efficient cache design in emerging mobile platforms. We observe that more than 40% of L2 cache accesses are OS kernel accesses in interactive smartphone applications. Such frequent kernel accesses cause serious interferences between the user and kernel blocks in the L2 cache, leading to unnecessary block replacements and high L2 cache miss rate. We first propose to statically partition the L2 cache into two separate segments, which can be accessed only by the user code and kernel code, respectively. Meanwhile, the overall size of the two segments is shrunk, which reduces the energy consumption while still maintaining the similar cache miss rate. We then find completely different access behaviors between the two separated kernel and user segments and explore the multi-retention STT-RAM-based user and kernel segments to obtain higher energy savings in this static partition-based cache design. Finally, we propose to dynamically partition the L2 cache into the user and kernel segments to minimize overall cache size. We also integrate the short-retention STT-RAM into this dynamic partition-based cache design for maximal energy savings. The experimental results show that our static technique reduces cache energy consumption by 75% with 2% performance loss, and our dynamic technique further shows strong capability to reduce cache energy consumption by 85% with only 3% performance loss.
Funder
NSF of China
NFS
State of Kansas through the Kansas Board of Regents
Publisher
Association for Computing Machinery (ACM)
Subject
Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Computer Science Applications
Cited by
4 articles.
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1. How to secure autonomous mobile robots? An approach with fuzzing, detection and mitigation;Journal of Systems Architecture;2021-01
2. Energy and Performance Analysis of STTRAM Caches for Mobile Applications;2019 IEEE 13th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC);2019-10
3. MH Cache;ACM Transactions on Architecture and Code Optimization;2019-09-30
4. Sleepy-LRU: extending the lifetime of non-volatile caches by reducing activity of age bits;The Journal of Supercomputing;2019-01-23