A hardware evaluation of cache partitioning to improve utilization and energy-efficiency while preserving responsiveness
Author:
Affiliation:
1. University of California, Berkeley
2. University of California, Berkeley and Universitat Politecnica de Catalunya, Jordi Girona, Barcelona, Spain
Funder
Nvidia
Intel Corporation
Agència de Gestió d'Ajuts Universitaris i de Recerca
Mountain Equipment Co-op
University of California
Samsung
Nokia
Microsoft
Oracle
Ministerio de Economía y Competitividad
MEC/Fulbright Fellowship
Publisher
ACM
Link
https://dl.acm.org/doi/pdf/10.1145/2485922.2485949
Reference37 articles.
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2. The DaCapo benchmarks
3. Predictable performance in SMT processors: synergy between the OS and SMTs
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