MLP+NeuroSimV3.0
Author:
Affiliation:
1. School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, Georgia, United States
Funder
NSF/SRC E2CDA program
Semiconductor Research Corporation
National Science Foundation
Publisher
ACM
Link
https://dl.acm.org/doi/pdf/10.1145/3354265.3354266
Reference22 articles.
1. Neuro-Inspired Computing With Emerging Nonvolatile Memorys
2. X. Si J.-J. Chen Y.-N. Tu W.-H. Huang J.-H. Wang W.-C. Wei S.-Y. Wu X. Sun R. Liu S. Yu R.-S. Liu C.-C. Hsieh K.-T. Tang Q. Li M.-F. Chang "A twin-8T SRAM computation-in-memory macro for multiple-bit CNN-based machine learning " IEEE International Solid-State Circuits Conference (ISSCC) 2019 X. Si J.-J. Chen Y.-N. Tu W.-H. Huang J.-H. Wang W.-C. Wei S.-Y. Wu X. Sun R. Liu S. Yu R.-S. Liu C.-C. Hsieh K.-T. Tang Q. Li M.-F. Chang "A twin-8T SRAM computation-in-memory macro for multiple-bit CNN-based machine learning " IEEE International Solid-State Circuits Conference (ISSCC) 2019
3. W. Chen K. Li W. Lin K. Hsu P. Li C. Yang C. Xue E. Yang Y. Chen Y. Chang T. Hsu Y. King C. Lin R. Liu C. Hsieh K. Tang and M. Chang. "A 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns multiply-and-accumulate for binary DNN AI edge processors " 2018 IEEE International Solid - State Circuits Conference - (ISSCC) San Francisco CA 2018 pp. 494--496. W. Chen K. Li W. Lin K. Hsu P. Li C. Yang C. Xue E. Yang Y. Chen Y. Chang T. Hsu Y. King C. Lin R. Liu C. Hsieh K. Tang and M. Chang. "A 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns multiply-and-accumulate for binary DNN AI edge processors " 2018 IEEE International Solid - State Circuits Conference - (ISSCC) San Francisco CA 2018 pp. 494--496.
4. Parallelizing SRAM arrays with customized bit-cell for binary neural networks
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