Parallelizing SRAM arrays with customized bit-cell for binary neural networks-Reference-Cited by-同舟云学术

Parallelizing SRAM arrays with customized bit-cell for binary neural networks

Published:2018-06-24 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 55th Annual Design Automation Conference
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Author:

Liu Rui¹,Peng Xiaochen¹,Sun Xiaoyu¹,Khwa Win-San²,Si Xin²,Chen Jia-Jing²,Li Jia-Fang²,Chang Meng-Fan²,Yu Shimeng¹

Affiliation:

1. Arizona State University

2. National Tsing Hua University, Hsinchu, Taiwan

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3195970.3196089

Reference14 articles.

1. K. Simonyan and A. Zisserman "Very deep convolutional networks for large-scale image recognition " in ICLR 2015. K. Simonyan and A. Zisserman "Very deep convolutional networks for large-scale image recognition " in ICLR 2015.

2. M. Courbariaux etal "Binarized neural network: Training deep neural networks with weights and activations constrained to+ 1 or-1 " arXiv: 1602.02830 2016. M. Courbariaux et al. "Binarized neural network: Training deep neural networks with weights and activations constrained to+ 1 or-1 " arXiv: 1602.02830 2016.

3. M. Rastegari etal "XNOR-Net: ImageNet classification using binary convolutional neural networks " arXiv: 1603.05279 2016. M. Rastegari et al. "XNOR-Net: ImageNet classification using binary convolutional neural networks " arXiv: 1603.05279 2016.

4. Y.-H. Chen etal "Eyeriss: an energy-efficient reconfigurable accelerator for deep convolutional neural networks " in IEEE ISSCC 2016. Y.-H. Chen et al. "Eyeriss: an energy-efficient reconfigurable accelerator for deep convolutional neural networks " in IEEE ISSCC 2016.

5. N. P. Jouppi etal "In-datacenter performance analysis of a Tensor Processing Unit " in ACM/IEEE ISCA 2017. 10.1145/3079856.3080246 N. P. Jouppi et al. "In-datacenter performance analysis of a Tensor Processing Unit " in ACM/IEEE ISCA 2017. 10.1145/3079856.3080246

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