A 9 Transistor SRAM Featuring Array-level XOR Parallelism with Secure Data Toggling Operation
Author:
Affiliation:
1. Electrical and Computer Engineering, University of Wisconsin-Madison, USA
2. University of Southern California, USA
3. Information Sciences Institute, USA
4. University of Wisconsin-Madison, USA
Publisher
ACM
Link
https://dl.acm.org/doi/pdf/10.1145/3649476.3658789
Reference24 articles.
1. X-SRAM: Enabling In-Memory Boolean Computations in CMOS Static Random Access Memories
2. In-Memory Computing with 6T SRAM for Multi-operator Logic Design
3. High-assurance processor active memory content protection;Furusawa Michael Masaji;US Patent,2014
4. Lest we remember
5. Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S Chang, and Ne Kyaw Zwa Lwin. 2014. A dynamic-voltage-scaling 1kbyte × 8-bit non-imprinting Master-Slave SRAM with high speed erase for low-power operation. In 2014 International Symposium on Integrated Circuits (ISIC). IEEE, 320–323.
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