A Fault-Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors

Author:

Mohammadi Hassan Ghasemzadeh1,Gaillardon Pierre-Emmanuel2,Zhang Jian1,Micheli Giovanni De1,Sanchez Ernesto3,Reorda Matteo Sonza3

Affiliation:

1. Ecole Polytechnique Fédérale de Lausanne (EPFL), Lausanne, Switzerland

2. University of Utah, UT, USA

3. Politecnico di Torino, Torino, Italy

Abstract

This article first explores the effects of faults on circuits implemented with controllable-polarity transistors. We propose a new fault model that suits the characteristics of these devices, and we report the results of a SPICE-based analysis of the effects of faults on the behavior of some basic gates implemented with them. Hence, we show that the considered devices are able to intrinsically tolerate a rather high number of faults. We finally exploit this property to build a robust and scalable adder whose area, performance, and leakage power characteristics are improved by 15%, 18%, and 12%;, respectively, when compared to an equivalent FinFET solution at 22nm technology node.

Funder

ERC senior

Publisher

Association for Computing Machinery (ACM)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

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