A Survey on Cache Management Mechanisms for Real-Time Embedded Systems

Author:

Gracioli Giovani1,Alhammad Ahmed2,Mancuso Renato3,Fröhlich Antônio Augusto1,Pellizzoni Rodolfo2

Affiliation:

1. Federal University of Santa Catarina, Brazil

2. University of Waterloo, Canada

3. University of Illinois at Urbana-Champaign

Abstract

Multicore processors are being extensively used by real-time systems, mainly because of their demand for increased computing power. However, multicore processors have shared resources that affect the predictability of real-time systems, which is the key to correctly estimate the worst-case execution time of tasks. One of the main factors for unpredictability in a multicore processor is the cache memory hierarchy. Recently, many research works have proposed different techniques to deal with caches in multicore processors in the context of real-time systems. Nevertheless, a review and categorization of these techniques is still an open topic and would be very useful for the real-time community. In this article, we present a survey of cache management techniques for real-time embedded systems, from the first studies of the field in 1990 up to the latest research published in 2014. We categorize the main research works and provide a detailed comparison in terms of similarities and differences. We also identify key challenges and discuss future research directions.

Publisher

Association for Computing Machinery (ACM)

Subject

General Computer Science,Theoretical Computer Science

Reference112 articles.

1. Aeronautical Radio Inc. 2013. Avionics Application Software Standard Interface: ARINC Specification 653 Part 0. Retrieved from https://www.arinc.com/cf/store/catalog_detail.cfm?item_id=2039. Aeronautical Radio Inc. 2013. Avionics Application Software Standard Interface: ARINC Specification 653 Part 0. Retrieved from https://www.arinc.com/cf/store/catalog_detail.cfm?item_id=2039.

2. Cache index-aware memory allocation

3. Performance evaluation of cache replacement policies for the SPEC CPU2000 benchmark suite

4. AMD. 2013. AMD64 Architecture Programmers Manual Volume 2: System Programming. Section 7.3: Memory Coherency and Protocol. Publication # 24593. Revision: 3.23. AMD. 2013. AMD64 Architecture Programmers Manual Volume 2: System Programming. Section 7.3: Memory Coherency and Protocol. Publication # 24593. Revision: 3.23.

5. Improving the WCET computation in the presence of a lockable instruction cache in multitasking real-time systems

Cited by 65 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Multi-criteria Optimization of Real-time DAGs on Heterogeneous Platforms under P-EDF;ACM Transactions on Embedded Computing Systems;2024-01-10

2. FASTA: Revisiting Fully Associative Memories in Computer Microarchitecture;IEEE Access;2024

3. Development of Low Power and Area Efficient Multi-core Memory Controller Using AXI4-Lite Interface Protocol;Studies in Autonomic, Data-driven and Industrial Computing;2024

4. CAMP: a hierarchical cache architecture for multi-core mixed criticality processors;International Journal of Parallel, Emergent and Distributed Systems;2023-12-19

5. A Survey of Memory-Centric Energy Efficient Computer Architecture;IEEE Transactions on Parallel and Distributed Systems;2023-10

同舟云学术

1.学者识别学者识别

2.学术分析学术分析

3.人才评估人才评估

"同舟云学术"是以全球学者为主线,采集、加工和组织学术论文而形成的新型学术文献查询和分析系统,可以对全球学者进行文献检索和人才价值评估。用户可以通过关注某些学科领域的顶尖人物而持续追踪该领域的学科进展和研究前沿。经过近期的数据扩容,当前同舟云学术共收录了国内外主流学术期刊6万余种,收集的期刊论文及会议论文总量共计约1.5亿篇,并以每天添加12000余篇中外论文的速度递增。我们也可以为用户提供个性化、定制化的学者数据。欢迎来电咨询!咨询电话:010-8811{复制后删除}0370

www.globalauthorid.com

TOP

Copyright © 2019-2024 北京同舟云网络信息技术有限公司
京公网安备11010802033243号  京ICP备18003416号-3