Affiliation:
1. Zhejiang University, Hangzhou, China
2. University of Notre Dame, IN, USA
Abstract
Cellular Neural Network (CeNN) is considered as a powerful paradigm for embedded devices. Its analog and mix-signal hardware implementations are proved to be applicable to high-speed image processing, video analysis, and medical signal processing with its efficiency and popularity limited by smaller implementation size and lower precision. Recently, digital implementations of CeNNs on FPGA have attracted researchers from both academia and industry due to its high flexibility and short time-to-market. However, most existing implementations are not well optimized to fully utilize the advantages of FPGA platform with unnecessary design and computational redundancy that prevents speedup. We propose a multi-level-optimization framework for energy-efficient CeNN implementations on FPGAs. In particular, the optimization framework is featured with three level optimizations: system-, module-, and design-space-level, with focus on computational redundancy and attainable performance, respectively. Experimental results show that with various configurations our framework can achieve an energy-efficiency improvement of 3.54× and up to 3.88× speedup compared with existing implementations with similar accuracy.
Publisher
Association for Computing Machinery (ACM)
Subject
Electrical and Electronic Engineering,Hardware and Architecture,Software
Reference33 articles.
1. From layout to system: Early stage power delivery and architecture co-exploration;Zhuo Cheng;IEEE Trans. Comput.-Aided Design Integr. Circ. Syst. PP,2018
2. Silicon-Validated Power Delivery Modeling and Analysis on a 32-nm DDR I/O Interface
3. Edge detection of noisy images based on cellular neural networks
4. Edge detection in satellite image using cellular neural network;Gazi Osama Basil;System,2014
Cited by
14 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献