Silicon-Validated Power Delivery Modeling and Analysis on a 32-nm DDR I/O Interface

Author:

Zhuo Cheng,Wilke Gustavo,Chakraborty Ritochit,Aydiner Alaeddin A.,Chakravarty Sourav,Shih Wei-Kai

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Cited by 11 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Agile Full-Chip Sign-Off in the Post-Moore Era;2023 China Semiconductor Technology International Conference (CSTIC);2023-06-26

2. A Fast Method to Estimate Through-Bump Current for Power Delivery Verification;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023-05

3. Worst-Case Power Integrity Prediction Using Convolutional Neural Network;ACM Transactions on Design Automation of Electronic Systems;2022-10-03

4. Worst-case dynamic power distribution network noise prediction using convolutional neural network;Proceedings of the 59th ACM/IEEE Design Automation Conference;2022-07-10

5. Application of Deep Learning in Back-End Simulation: Challenges and Opportunities;2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC);2022-01-17

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