1. Process Variability for Devices at and beyond the 7 nm Node
2. Computational Complexity of Test-Point Insertions and Decompositions
3. Y. Sun , and S. Millican . " Test point insertion using artificial neural networks." In 2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) , pp. 253 -- 258 . IEEE , 2019 . Y. Sun, and S. Millican. "Test point insertion using artificial neural networks." In 2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 253--258. IEEE, 2019.
4. T.N. Kipf and M. Welling . " Semi-supervised classification with graph convolutional networks." arXiv preprint arXiv:1609.02907 ( 2016 ). T.N. Kipf and M. Welling. "Semi-supervised classification with graph convolutional networks." arXiv preprint arXiv:1609.02907 (2016).
5. A. Mirhoseini A. Goldie M. Yazgan J. Jiang E. Songhori S. Wang Y.-J. Lee. "Chip placement with deep reinforcement learning." arXiv preprint arXiv:2004.10746 (2020). A. Mirhoseini A. Goldie M. Yazgan J. Jiang E. Songhori S. Wang Y.-J. Lee. "Chip placement with deep reinforcement learning." arXiv preprint arXiv:2004.10746 (2020).