1. T. Thorolfsson , G. Luo , J. Cong and P. D. Franzon , " Logic-on-logic 3D integration and placement," 2010 IEEE International 3D Systems Integration Conference (3DIC) , 2010 , pp. 1 -- 4 T. Thorolfsson, G. Luo, J. Cong and P. D. Franzon, "Logic-on-logic 3D integration and placement," 2010 IEEE International 3D Systems Integration Conference (3DIC), 2010, pp. 1--4
2. J. Kim GDS Design Tools for Monolithic 3 D I Cs ," 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD) , 2020 , pp. 1 -- 8 . J. Kim et al., "RTL-to-GDS Design Tools for Monolithic 3D ICs," 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2020, pp. 1--8.
3. S. S. Kiran Pentapati , K. Chang , V. Gerousis , R. Sengupta and S. K. Lim , " Pin-3D: A Physical Synthesis and Post-Layout Optimization Flow for Heterogeneous Monolithic 3D ICs," 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD) , 2020 , pp. 1 -- 9 . S. S. Kiran Pentapati, K. Chang, V. Gerousis, R. Sengupta and S. K. Lim, "Pin-3D: A Physical Synthesis and Post-Layout Optimization Flow for Heterogeneous Monolithic 3D ICs," 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2020, pp. 1--9.
4. Compact-2D: A Physical Design Methodology to Build Two-Tier Gate-Level 3-D ICs
5. 2022 ICCAD CAD Contest Problem B: http://iccad-contest.org/Problems.html 2022 ICCAD CAD Contest Problem B: http://iccad-contest.org/Problems.html