TA3D: Timing-Aware 3D IC Partitioning and Placement by Optimizing the Critical Path
Author:
Affiliation:
1. Department of Electrical Engineering, Pohang University of Science and Technology, Pohang, Republic of Korea
2. Baum Design Systems Co., Seoul, Republic of Korea
Publisher
ACM
Link
https://dl.acm.org/doi/pdf/10.1145/3670474.3685957
Reference27 articles.
1. 2022 ICCAD CAD Contest Problem B
2. Recent advances and trends in Cu-Cu hybrid bonding;Lau John H;IEEE TCPMT,2023
3. Three-dimensional wafer stacking via Cu-Cu bonding integrated with 65-nm strained-Si/low-k CMOS technology
4. The 3-D Interconnect Technology Landscape
5. Beyne, Eric, et al., "Scalable, sub 2μm pitch, Cu/SiCN to Cu/SiCN hybrid wafer-to-wafer bonding technology," In Proc. IEDM, pp. 32--4, 2017.
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