A Novel DRAM-Based Process-in-Memory Architecture and its Implementation for CNNs-Reference-Cited by-同舟云学术

A Novel DRAM-Based Process-in-Memory Architecture and its Implementation for CNNs

Published:2021-01-18 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 26th Asia and South Pacific Design Automation Conference
language:
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Author:

Sudarshan Chirag¹,Soliman Taha²,De la Parra Cecilia²,Weis Christian¹,Ecco Leonardo²,Jung Matthias³,Wehn Norbert¹,Guntoro Andre²

Affiliation:

1. Microelectronic Systems Design, Research Group, TU Kaiserslautern, Kaiserslautern, Germany

2. Robert Bosch GmbH - Corporate Research (CR/ADT2), Stuttgart, Germany

3. Fraunhofer Institute for Experimental, Software Engineering (IESE), Kaiserslautern, Germany

Funder

Horizon 2020 Framework Programme

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3394885.3431522

Reference31 articles.

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2. Eyeriss

3. Y. Chen et al. 2019. Eyeriss v2: A Flexible Accelerator for Emerging Deep Neural Networks on Mobile Devices. IEEE Journal on Emerging and Selected Topics in Circuits and Systems (2019). Y. Chen et al. 2019. Eyeriss v2: A Flexible Accelerator for Emerging Deep Neural Networks on Mobile Devices. IEEE Journal on Emerging and Selected Topics in Circuits and Systems (2019).

4. Jeongdong Choe. 2017. Samsung 18 nm DRAM cell integration: QPT and higher uniformed capacitor high-k dielectrics. https://www.techinsights.com/blog/samsung-18-nm-dram-cell-integration-qpt-and-higher-uniformed-capacitor-high-k-dielectrics Jeongdong Choe. 2017. Samsung 18 nm DRAM cell integration: QPT and higher uniformed capacitor high-k dielectrics. https://www.techinsights.com/blog/samsung-18-nm-dram-cell-integration-qpt-and-higher-uniformed-capacitor-high-k-dielectrics

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