Affiliation:
1. National Chiao Tung University, Hsinchu, Taiwan
2. Cadence Design Systems, Taiwan
Abstract
Device aging, which causes significant loss on circuit performance and lifetime, has been a primary factor in reliability degradation of nanoscale designs. In this article, we propose to take advantage of aging-induced clock skews (i.e., make them useful for aging tolerance) by manipulating and recycling these time-varying skews to compensate for the performance degradation of logic networks. The goal is to assign achievable/reasonable aging-induced clock skews in a circuit, such that its effective performance degradation due to aging can be tolerated. On average, 21.21% aging tolerance can be achieved with insignificant design overhead. Moreover, we employ
V
th
assignment on clock buffers to further tolerate the aging-induced degradation of logic networks. When
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th
assignment is applied on top of aforementioned aging manipulation, the average aging tolerance can be enhanced to 29.15%.
Funder
National Chiao Tung University
Ministry of Education
Publisher
Association for Computing Machinery (ACM)
Subject
Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Computer Science Applications
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