Congestion reduction during placement with provably good approximation bound

Author:

Yang X.1,Wang M.2,Kastner R.3,Ghiasi S.4,Sarrafzadeh M.4

Affiliation:

1. Synplicity, Inc., Sunnyvale, CA

2. Cadence Design Systems, Inc., San Jose, CA

3. University of California, Santa Barbara, CA

4. University of California, Los Angeles, CA

Abstract

This paper presents a novel method to reduce routing congestion during placement stage. The proposed approach is used as a post-processing step in placement. Congestion reduction is based on local improvement on the existing layout. However, the approach has a global view of the congestion over the entire design. It uses integer linear programming (ILP) to formulate the problem of conflicts between multiple congested regions, and performs local improvement according to the solution of the ILP problem. The approximation algorithm of the formulated ILP problem is studied and good approximation bounds are given and proved. Experiments show that the proposed approach can effectively alleviate the congestion of global routing results. The low computational complexity of the proposed approach indicates its scalability on large designs.

Publisher

Association for Computing Machinery (ACM)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Computer Science Applications

Reference17 articles.

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2. Cong J. and Madden P. 1998. "Performance Driven Multi-Layer General Area Routing for PCB/MCM Designs." In Design Automation Conference pages 356--361. 10.1145/277044.277144 Cong J. and Madden P. 1998. "Performance Driven Multi-Layer General Area Routing for PCB/MCM Designs." In Design Automation Conference pages 356--361. 10.1145/277044.277144

3. A Procedure for Placement of Standard Cell VLSI Circuits;Dunlop A. E.;IEEE Trans. Comput. Aided Design,1985

4. ERLAB(a). "IBM-PLACE benchmark." http://er.cs.ucla.edu/benchmarks/ibm-place/. ERLAB(a). "IBM-PLACE benchmark." http://er.cs.ucla.edu/benchmarks/ibm-place/.

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