SAINT
Author:
Affiliation:
1. Kung University, Tainan, Taiwan
2. National Cheng Kung University, Tainan, Taiwan
Publisher
ACM
Link
https://dl.acm.org/doi/pdf/10.1145/2966986.2967071
Reference35 articles.
1. CELONCEL: Effective Design Technique for 3-D Monolithic Integration Targeting High Performance Integrated Circuits;Bobba S.;Proc. ASP-DAC, pages,2011
2. Floorplan sizing by linear programming approximation
3. Floorplanning for 3-D VLSI design
4. NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs With Preplaced Blocks and Density Constraints
5. Multi-layer floorplanning for stacked ICs: Configuration number and fixed-outline constraints
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1. A Novel Thermal-Aware Floorplanning and TSV Assignment With Game Theory for Fixed-Outline 3-D ICs;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023-11
2. Routability-Driven Orientation-Aware Analytical Placement for System in Package;2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD);2023-10-28
3. Handling Orientation and Aspect Ratio of Modules in Electrostatics-Based Large Scale Fixed-Outline Floorplanning;2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD);2023-10-28
4. Best of both worlds;Proceedings of the International Conference on Computer-Aided Design;2018-11-05
5. A fast thermal-aware fixed-outline floorplanning methodology based on analytical models;Proceedings of the International Conference on Computer-Aided Design;2018-11-05
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