Joint loop mapping and data placement for coarse-grained reconfigurable architecture with multi-bank memory-Reference-Cited by-同舟云学术

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Joint loop mapping and data placement for coarse-grained reconfigurable architecture with multi-bank memory

Published:2016-11-07 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 35th International Conference on Computer-Aided Design
language:
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Author:

Yin Shouyi¹,Yao Xianqing¹,Lu Tianyi¹,Liu Leibo¹,Wei Shaojun¹

Affiliation:

1. Tsinghua University, Beijing, China

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/2966986.2967049

Reference10 articles.

1. Force-directed scheduling for Data Flow Graph mapping on Coarse-Grained Reconfigurable Architectures

2. EPIMap

3. REGIMap

4. Operation and data mapping for CGRAs with multi-bank memory

5. High Throughput Data Mapping for Coarse-Grained Reconfigurable Architectures

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1. Complete Reconfigurable Boolean Logic Gates Based on One FeFET -One RRAM Technology;ESSDERC 2023 - IEEE 53rd European Solid-State Device Research Conference (ESSDERC);2023-09-11

2. Coarse-Grained Reconfigurable Array (CGRA);Handbook of Computer Architecture;2022-11-25

3. RF-CGRA: A Routing-Friendly CGRA with Hierarchical Register Chains;2022 Design, Automation & Test in Europe Conference & Exhibition (DATE);2022-03-14

4. CASCADE;ACM Transactions on Embedded Computing Systems;2019-10-19

5. Coarse Grained Reconfigurable Architecture Loop Mapping Algorithm Based on Memory Partitioning and Path Reuse;J ELECTRON INF TECHN;2018

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