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High Throughput Data Mapping for Coarse-Grained Reconfigurable Architectures

  • Published:2011-11 Issue:11 Volume:30 Page:1599-1609
  • ISSN:0278-0070
  • Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
  • language:
  • Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Author:

Yongjoo Kim ,Jongeun Lee ,Shrivastava A.,Yoon J. W.,Doosan Cho ,Yunheung Paek

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Cited by 26 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Reschedulable Dataflow-SIMD Execution for Increased Utilization in CGRA Cross-Domain Acceleration;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023-03

2. Hardware Acceleration of Sparse and Irregular Tensor Computations of ML Models: A Survey and Insights;Proceedings of the IEEE;2021-10

3. Reducing Memory Access Conflicts with Loop Transformation and Data Reuse on Coarse-grained Reconfigurable Architecture;2021 Design, Automation & Test in Europe Conference & Exhibition (DATE);2021-02-01

4. Specializing CGRAs for Light-Weight Convolutional Neural Networks;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2021

5. dMazeRunner: Optimizing Convolutions on Dataflow Accelerators;ICASSP 2020 - 2020 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP);2020-05
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