Affiliation:
1. University of Washington
Abstract
Tiled architectures, such as RAW, SmartMemories, TRIPS, and WaveScalar, promise to address several issues facing conventional processors, including complexity, wire-delay, and performance. The basic premise of these architectures is that larger, higher-performance implementations can be constructed by replicating the basic tile across the chip. This paper explores the area-performance trade-offs when designing one such tiled architecture, WaveScalar. We use a synthesizable RTL model and cycle-level simulator to perform an area/performance pareto analysis of over 200 WaveScalar processor designs ranging in size from 19mm2 to 378mm2 and having a 22 FO4 cycle time. We demonstrate that, for multi-threaded workloads, WaveScalar performance scales almost ideally from 19 to 101mm2 when optimized for area efficiency and from 44 to 202mm2when optimized for peak performance. Our analysis reveals that WaveScalar's hierarchical interconnect plays an important role in overall scalability, and that WaveScalar achieves the same (or higher) performance in substantially less area than either an aggressive out-of-order superscalar or Sun's Niagara CMP processor.
Publisher
Association for Computing Machinery (ACM)
Reference31 articles.
1. {1} W. Lee et al. "Space-time scheduling of instruction-level parallelism on a Raw machine " in Proceedings of the 8th International Conference on Architectural Support for Programming Languages and Operating Systems ASPLOS-VIII October 1998. 10.1145/291069.291018 {1} W. Lee et al. "Space-time scheduling of instruction-level parallelism on a Raw machine " in Proceedings of the 8th International Conference on Architectural Support for Programming Languages and Operating Systems ASPLOS-VIII October 1998. 10.1145/291069.291018
2. Smart Memories
3. {3} R. Nagarajan K. Sankaralingam D. Burger and S. Keckler "A design space evaluation of grid processor architectures " in Proceedings of the 34th Annual International Symposium on Microarchitecture 2001. {3} R. Nagarajan K. Sankaralingam D. Burger and S. Keckler "A design space evaluation of grid processor architectures " in Proceedings of the 34th Annual International Symposium on Microarchitecture 2001.
4. {4} K. Sankaralingam R. Nagarajan H. Liu C. Kim J. Huh D. Burger S. W. Keckler and C. R. Moore "Exploiting ILP TLP and DLP with the polymorphous TRIPS architecture " in Proceedings of the 30th annual international symposium on Computer architecture 2003. 10.1145/859618.859667 {4} K. Sankaralingam R. Nagarajan H. Liu C. Kim J. Huh D. Burger S. W. Keckler and C. R. Moore "Exploiting ILP TLP and DLP with the polymorphous TRIPS architecture " in Proceedings of the 30th annual international symposium on Computer architecture 2003. 10.1145/859618.859667
5. {5} S. Swanson K. Michelson A. Schwerin and M. Oskin "WaveScalar " in Proceedings of the 36th Annual IEEE/ACM International Symposium on Microarchitecture p. 291 2003. {5} S. Swanson K. Michelson A. Schwerin and M. Oskin "WaveScalar " in Proceedings of the 36th Annual IEEE/ACM International Symposium on Microarchitecture p. 291 2003.
Cited by
3 articles.
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