Author:
Beck Antonio Carlos S.,Rutzig Mateus B.,Gaydadjiev Georgi,Carro Luigi
Cited by
7 articles.
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1. Potential analysis of a superscalar core employing a reconfigurable array for improving instruction-level parallelism;Design Automation for Embedded Systems;2016-03-17
2. DynaSpAM;ACM SIGARCH Computer Architecture News;2016-01-04
3. DynaSpAM;Proceedings of the 42nd Annual International Symposium on Computer Architecture;2015-06-13
4. A Reconfigurable Architecture for Binary Acceleration of Loops with Memory Accesses;ACM Transactions on Reconfigurable Technology and Systems;2015-01-23
5. Reconfigurable Memories;Adaptable Embedded Systems;2012-10-20