Low Area, Low Power, Robust, Highly Sensitive Error Detecting Latch for Resilient Architectures

Author:

Hua Weizhe1,Tadros Ramy N.1,Beerel Peter A.1

Affiliation:

1. University of Southern California - Los Angeles, CA

Publisher

ACM

Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Negative Design Margin Realization through Deep Path Activity Detection Combined with Dynamic Voltage Scaling in a 55 nm Near-Threshold 32-Bit Microcontroller;Sensors;2023-08-29

2. SERAD: Soft Error Resilient Asynchronous Design Using a Bundled Data Protocol;IEEE Transactions on Circuits and Systems I: Regular Papers;2020-05

3. Testing the blade resilient asynchronous template;Analog Integrated Circuits and Signal Processing;2020-04-23

4. A Near-Threshold Spiking Neural Network Accelerator With a Body-Swapping-Based $In \,\,Situ$ Error Detection and Correction Technique;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2019-08

5. Area Optimization of Timing Resilient Designs Using Resynthesis;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2018-06

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