Capturing dynamic memory reference behavior with adaptive cache topology

Author:

Peir Jih-Kwon1,Lee Yongjoon1,Hsu Windsor W.2

Affiliation:

1. Computer & Information Science & Engineering Department, University of Florida, Gainesville, FL

2. Computer Science Division, University of California, Berkeley, CA

Abstract

Memory references exhibit locality and are therefore not uniformly distributed across the sets of a cache. This skew reduces the effectiveness of a cache because it results in the caching of a considerable number of less-recently-used lines which are less likely to be re-referenced before they are replaced. In this paper, we describe a technique that dynamically identifies these less-recently-used lines and effectively utilizes the cache frames they occupy to more accurately approximate the global least-recently-used replacement policy while maintaining the fast access time of a direct-mapped cache. We also explore the idea of using these underutilized cache frames to reduce cache misses through data prefetching. In the proposed design, the possible locations that a line can reside in is not predetermined. Instead, the cache is dynamically partitioned into groups of cache lines. Because both the total number of groups and the individual group associativity adapt to the dynamic reference pattern, we call this design the adaptive group-associative cache. Performance evaluation using trace-driven simulations of the TPC-C benchmark and selected programs from the SPEC95 benchmark suite shows that the group-associative cache is able to achieve a hit ratio that is consistently better than that of a 4-way set-associative cache. For some of the workloads, the hit ratio approaches that of a fully-associative cache.

Publisher

Association for Computing Machinery (ACM)

Subject

Computer Graphics and Computer-Aided Design,Software

Cited by 4 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A Self-Reconfiguring Cache Architecture to Improve Control Quality in Cyber-Physical Systems;2018 IEEE 21st International Symposium on Real-Time Distributed Computing (ISORC);2018-05

2. Image-Optimized Rolling Cache: Reducing the Miss Penalty for Memory-Intensive Vision Algorithms;IEEE Transactions on Circuits and Systems for Video Technology;2014-03

3. Adaptive Selection of Cache Indexing Bits for Removing Conflict Misses;IEEE Transactions on Computers;2014

4. A comparative analysis of performance improvement schemes for cache memories;Computers & Electrical Engineering;2012-03

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