Design of 0.6v 0.01mm2 Sub Sampling PLL Based On Dynamic Double Loops
Author:
Affiliation:
1. Nanjing Meichen Microelectronics, Nanjing Meichen Microelectronics, China
2. Nanjing Research Institute of Electronic Technology, China
3. School of Cyber Science and Engineering, Southeast University, China
Publisher
ACM
Link
https://dl.acm.org/doi/pdf/10.1145/3531028.3531043
Reference17 articles.
1. A 0.5-V 0.4–2.24-GHz Inductorless Phase-Locked Loop in a System-on-Chip
2. A Fully Synthesizable Fractional-N MDLL With Zero-Order Interpolation-Based DTC Nonlinearity Calibration and Two-Step Hybrid Phase Offset Calibration
3. A Fully-Synthesizable Fractional-N Injection-Locked PLL for Digital Clocking with Triangle/Sawtooth Spread-Spectrum Modulation Capability in 5-nm CMOS
4. A 0.0043-mm2 0.3–1.2-V Frequency-Scalable Synthesized Fractional-N Digital PLL With a Speculative Dual-Referenced Interpolating TDC
5. A 0.016 mm2 0.26-$\mu$ W/MHz 60–240-MHz Digital PLL With Delay-Modulating Clock Buffer in 65 nm CMOS
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