Architecture, Chip, and Package Co-design Flow for 2.5D IC Design Enabling Heterogeneous IP Reuse-Reference-Cited by-同舟云学术

Architecture, Chip, and Package Co-design Flow for 2.5D IC Design Enabling Heterogeneous IP Reuse

Published:2019-06-02 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 56th Annual Design Automation Conference 2019
language:
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Author:

Kim Jinwoo¹,Murali Gauthaman¹,Park Heechun¹,Qin Eric¹,Kwon Hyoukjun¹,Chaitanya Venkata¹,Chekuri Krishna¹,Dasari Nihar¹,Singh Arvind¹,Lee Minah¹,Torun Hakki Mert¹,Roy Kallol¹,Swaminathan Madhavan¹,Mukhopadhyay Saibal¹,Krishna Tushar¹,Lim Sung Kyu¹

Affiliation:

1. School of ECE, Georgia Institute of Technology, Atlanta, GA

Funder

Defense Advanced Research Projects Agency

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3316781.3317775

Reference4 articles.

1. opensmart: Single-cycle multi-hop noc generator in bsv and chisel. opensmart: Single-cycle multi-hop noc generator in bsv and chisel.

2. Assembly and reliability challenges in 3D integration of 28nm FPGA die on a large high density 65nm passive interposer

3. Floorplanning and Signal Assignment for Silicon Interposer-based 3D ICs

4. Cost analysis and cost-driven IP reuse methodology for SoC design based on 2.5D/3D integration

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