Thread Weaving-Reference-Cited by-同舟云学术

Thread Weaving

Published:2019-06-02 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 56th Annual Design Automation Conference 2019
language:
Short-container-title:

Author:

Hsiao Hsuan¹,Anderson Jason¹

Affiliation:

1. University of Toronto

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3316781.3317924

Reference11 articles.

1. A. Canis S. D. Brown and J. H. Anderson. 2014. Modulo SDC scheduling with recurrence minimization in high-level synthesis. In FPL. A. Canis S. D. Brown and J. H. Anderson. 2014. Modulo SDC scheduling with recurrence minimization in high-level synthesis. In FPL.

2. LegUp

3. J. Choi S. Brown and J. Anderson. 2015. Resource and memory management techniques for the high-level synthesis of software threads into parallel FPGA hardware. In IEEE FPT. 152--159. J. Choi S. Brown and J. Anderson. 2015. Resource and memory management techniques for the high-level synthesis of software threads into parallel FPGA hardware. In IEEE FPT. 152--159.

4. J. Choi S. D. Brown and J. H. Anderson. 2013. From software threads to parallel hardware in high-level synthesis for FPGAs. In IEEE FPT. 270--277. J. Choi S. D. Brown and J. H. Anderson. 2013. From software threads to parallel hardware in high-level synthesis for FPGAs. In IEEE FPT. 270--277.

5. S. Hadjis etal 2012. Impact of FPGA Architecture on Resource Sharing in High-level Synthesis. In ACM FPGA. 111--114. 10.1145/2145694.2145712 S. Hadjis et al. 2012. Impact of FPGA Architecture on Resource Sharing in High-level Synthesis. In ACM FPGA. 111--114. 10.1145/2145694.2145712

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