Energy Efficient Runahead Execution on a Tightly Coupled Heterogeneous Core

Author:

Mashimo Susumu1,Shioya Ryota2,Inoue Koji1

Affiliation:

1. Kyushu University, Japan

2. The University of Tokyo, Japan

Publisher

ACM

Reference21 articles.

1. An Evaluation of High-Level Mechanistic Core Models

2. Intel Corporation. 2008. First the tick now the tock: next generation Intel microarchitecture (Nehalem). Intel Corporation. 2008. First the tick now the tock: next generation Intel microarchitecture (Nehalem).

3. NVIDIA Corporation. 2011. Variable SMP - a multi-core CPUarchitecture for low power and high performance. NVIDIA Corporation. 2011. Variable SMP - a multi-core CPUarchitecture for low power and high performance.

4. Filtered runahead execution with a runahead buffer

5. iCFP: Tolerating all-level cache misses in in-order processors

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