A New Algorithm for VHDL Parallel Simulation

Abstract

This article proposes a new algorithm for parallel synchronous simulation of VHDL designs to be executed on desktop computers. Besides executing VHDL processes in parallel, the algorithm focuses on parallelizing the simulation kernel with special emphasis on signal grouping while maintaining language semantics. Synchronous approaches are the most suitable for shared memory multiprocessor (SMP) desktop computers but may be difficult to parallelize because of the low activity detected in most of the designs. The degree of parallelism is increased in this approach by performing an exhaustive VHDL signal dependencies analysis and avoiding any sequential phase in the simulator. VHDL semantics impose a synchronization barrier after each phase, that is, the process and the kernel simulation phase, as the language definition does not allow simultaneous execution of kernel and processes. These barriers have been relaxed in order to increase the level of parallelism and obtain better performance. Another aspect the new algorithm takes into account is to improve load balancing and locality of references, both critical issues in synchronous simulators, by introducing a new load balancing algorithm that exploits the cyclic characteristics of circuit simulators. These developments make the algorithm suitable for commodity hardware, that is, SMP that are currently used as desktop personal computers.