Affiliation:
1. Department of Computer Science, The University of Manchester, Oxford Rd, Manchester, UK
Abstract
With FPGAs now being deployed in the cloud and at the edge, there is a need for scalable design methods that can incorporate the heterogeneity present in the hardware and software components of FPGA systems. Moreover, these FPGA systems need to be maintainable and adaptable to changing workloads while improving accessibility for the application developers. However, current FPGA systems fail to achieve modularity and support for multi-tenancy due to dependencies between system components and the lack of standardised abstraction layers. To solve this, we introduce a modular FPGA operating system – FOS, which adopts a modular FPGA development flow to allow each system component to be changed and be agnostic to the heterogeneity of EDA tool versions, hardware and software layers. Further, to dynamically maximise the utilisation transparently from the users, FOS employs resource-elastic scheduling to arbitrate the FPGA resources in both time and spatial domain for any type of accelerators. Our evaluation on different FPGA boards shows that FOS can provide performance improvements in both single-tenant and multi-tenant environments while substantially reducing the development time and, at the same time, improving flexibility.
Funder
European Commission under the H2020 Program and the EuroEXA project
UK Research Institute in Secure Hardware and Embedded Systems (RISE) through the project rFAS - reconfigurable FPGA Accelerator Sandboxing
Publisher
Association for Computing Machinery (ACM)
Cited by
23 articles.
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1. Flexible Updating of Internet of Things Computing Functions through Optimizing Dynamic Partial Reconfiguration;ACM Transactions on Embedded Computing Systems;2024-02
2. AFOCL: Portable OpenCL Programming of FPGAs via Automated Built-in Kernel Management;2023 IEEE Nordic Circuits and Systems Conference (NorCAS);2023-10-31
3. Efficient Resource Scheduling for Runtime Reconfigurable Systems on FPGAs;2023 33rd International Conference on Field-Programmable Logic and Applications (FPL);2023-09-04
4. ZyPR: End-to-end Build Tool and Runtime Manager for Partial Reconfiguration of FPGA SoCs at the Edge;ACM Transactions on Reconfigurable Technology and Systems;2023-06-21
5. Reconfigurable Virtual Memory for FPGA-Driven I/O;Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 3;2023-03-25