Compile-Time Silent-Store Elimination for Energy Efficiency-Reference-Cited by-同舟云学术

Compile-Time Silent-Store Elimination for Energy Efficiency

Published:2018 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the Rapido'18 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools - RAPIDO '18
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Author:

Bouziane Rabab¹,Rohou Erven¹,Gamatié Abdoulaye²

Affiliation:

1. Univ Rennes, Inria, CNRS, IRISA, Campus de Beaulieu, France

2. CNRS, LIRMM, Univ. Montpllier, Montpellier, France

Publisher

ACM Press

Reference31 articles.

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3. Nathan Binkert, Bradford Beckmann, Gabriel Black, Steven K. Reinhardt, Ali Saidi, Arkaprava Basu, Joel Hestness, Derek R. Hower, Tushar Krishna, Somayeh Sardashti, Rathijit Sen, Korey Sewell, Muhammad Shoaib, Nilay Vaish, Mark D. Hill, and David A. Wood. The gem5 simulator. SIGARCH Comput. Archit. News, 39(2):1--7, August 2011.

4. Shuai Che, Jeremy W. Sheaffer, Michael Boyer, Lukasz G. Szafaryn, Liang Wang, and Kevin Skadron. A characterization of the rodinia benchmark suite with comparison to contemporary CMP workloads. In International Symposium on Workload Characterization (IISWC'10), 2010.

5. Wei-Kai Cheng, Yen-Heng Ciou, and Po-Yuan Shen. Architecture and data migration methodology for L1 cache design with hybrid SRAM and volatile STT-RAM configuration. Microprocessors and Microsystems, 42, 2016.

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