Architecture and data migration methodology for L1 cache design with hybrid SRAM and volatile STT-RAM configuration

Author:

Cheng Wei-Kai,Ciou Yen-Heng,Shen Po-Yuan

Funder

National Science Council of Taiwan, R.O.C.

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Software

Reference25 articles.

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2. Advances and future prospects of spin-transfer torque random access memory;Chen;IEEE Trans. Magn.,2010

3. A novel nonvolatile memory with spin torque transfer magnetization switching: SPIN-RAM;Hosomi,2005

4. STT-RAM cell optimization considering MTJ and CMOS variations;Zhang;IEEE Trans. Magn.,2011

5. Power-aware variable partitioning for DSPs with hybrid PRAM and DRAM main memory;Liu;IEEE Trans. Signal Process.,2013

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1. Evaluating the performance and energy of STT-RAM caches for real-world wearable workloads;Future Generation Computer Systems;2022-11

2. Large-capacity and high-speed instruction cache based on divide-by-2 memory banks;Journal of Electronic Science and Technology;2021-12

3. Integer linear programming model for allocation and migration of data blocks in the STT‐RAM‐based hybrid caches;IET Computers & Digital Techniques;2020-02-10

4. Proactive useless data flush architecture for nonvolatile SRAM using magnetic tunnel junctions;IEICE Electronics Express;2020

5. ARC;Proceedings of the International Symposium on Memory Systems;2019-09-30

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