Author:
Lu Yongqiang,Sze C. N.,Hong Xianlong,Zhou Qiang,Cai Yici,Huang Liang,Hu Jiang
Cited by
5 articles.
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1. Clock Aware Low Power Placement;2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD);2023-10-28
2. Power Consumption in CMOS Circuits;Electromagnetic Field in Advancing Science and Technology;2023-03-29
3. A novel PDWC-UCO algorithm-based buffer placement in FPGA architecture;International Journal of Circuit Theory and Applications;2016-10-24
4. Flip-flop clustering by weighted K-means algorithm;Proceedings of the 53rd Annual Design Automation Conference;2016-06-05
5. Crosstalk-aware multi-bit flip-flop generation for power optimization;Integration;2015-01