Multiprocessor cache synchronization: issues, innovations, evolution

Author:

Bitar P.1,Despain A. M.2

Affiliation:

1. Research Institute for Advanced Computer Science, NASA Ames Research Center, Moffett Field, CA and Computer Science Division, University of California, Berkeley, CA

2. Computer Science Division, University of California, Berkeley, CA

Abstract

Many options are possible in a cache synchronization (or consistency) scheme for a broadcast system. We clarify basic concepts, analyze the handling of shared data, and then describe a protocol that we are currently exploring. Finally, we analyze the evolution of options that have been proposed under write-in (or write-back) policy. We show how our protocol extends this evolution with new methods for efficient busy-wait locking, waiting, and unlocking. The lock scheme allows locking and unlocking to occur in zero time, eliminating the need for test-and-set. The scheme also integrates processor atomic read-modify-write instructions and programmer/compiler busy-wait-synchronized operations under the same mechanism. The wait scheme eliminates all unsuccessful retries from the bus, and allows a process to work while waiting.

Publisher

Association for Computing Machinery (ACM)

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