Locally parallel cache design based on KL1 memory access characteristics-Reference-Cited by-同舟云学术

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Locally parallel cache design based on KL1 memory access characteristics

Published:1991-06 Issue:2 Volume:9 Page:149-169
ISSN:0288-3635
Container-title:New Generation Computing
language:en
Short-container-title:New Gener Comput

Author:

Matsumoto Akira,Nakagawa Takayuki,Sato Masatoshi,Kimura Yasunori,Nishida Kenji,Goto Atsuhiro

Publisher

Springer Science and Business Media LLC

Subject

Computer Networks and Communications,Hardware and Architecture,Theoretical Computer Science,Software

Link

http://link.springer.com/content/pdf/10.1007/BF03037641.pdf

Reference17 articles.

1. Archibald, J. and Baer, J., “Cache Coherence Protocols: Evaluation Using a Multiprocessor Simulation Model,”ACM Transaction of Computer Systems, 4, 4, pp. 273–298, 1986.

2. Bitar, P. and Despain, A. M., “Multiprocessor Cache Synchronization,” inProc. of the 13th Annual International Symposium on Computer Architecture, pp. 424–433, June, 1986.

3. Eggers, S. J. and Katz, R. H., “A Characterization of Sharing in Parallel Programs and Its Application to Coherency Protocol Evaluation,” inProc. of the 15th Annual International Symposium on Computer Architecture, pp. 373–382, June, 1988.

4. Goodman, J. R., “Using Cache Memory to Reduce Processor-Memory Traffic,” inProc. of the 10th Annual International Symposium on Computer Architecture, pp. 124–131, 1983.

5. Goto, A., “Parallel Inference Machine Research in FGCS Project,” inUS-Japan AI Symposium 87, pp. 21–36, Nov., 1987.

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