Using an oracle to measure potential parallelism in single instruction stream programs

Author:

Nicolau Alexandru,Fisher Joseph A.

Abstract

Horizontally microprogrammable CPUs belong to a class of machines having statically schedulable parallel instruction execution (SPIE machines). Several experiments have shown that within basic blocks, real code only gives a potential speed-up factor of 2 or 3 when compacted for SPIE machines, even in the presence of unlimited hardware. In this paper, similar experiments are described. However, these measure the potential parallelism available using any global compaction method, that is, one which compacts code beyond block boundaries. Global compaction is a subject of current investigation; no measurements yet exist on implemented systems. The approach taken is to first assume that an oracle is available during compaction. This oracle can resolve all dynamic considerations in advance, giving us the ability to find the maximum parallelism available without reformulation of the algorithm. The parallelism found is constrained only by legitimate data dependencies, since questions of conditional jump directions and unresolved indirect memory references are answered by the oracle. Using such an oracle, we find that typical scientific programs may be sped up by anywhere from 3 to 1000 times. These dramatic results provide an upper bound for global compaction techniques. We describe experiments in progress which attempt to limit the oracle progressively, with the aim of eventually producing one which provides only information that may be obtained by a very good compiler. This will give us a more practical measure of the parallelism potentially obtainable via global compaction methods.

Publisher

Association for Computing Machinery (ACM)

Reference9 articles.

Cited by 7 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Trace Scheduling;Instruction Level Parallelism;2016

2. A scalable architecture for ordered parallelism;Proceedings of the 48th International Symposium on Microarchitecture;2015-12-05

3. Customizing VLIW processors from dynamically profiled execution traces;Microprocessors and Microsystems;2015-11

4. Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures;International Journal of Parallel Programming;2007-05-25

5. The multiflow trace scheduling compiler;The Journal of Supercomputing;1993-05

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